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Change VHDL testbench and 32bit-ALU with clock to one without

Change VHDL testbench and 32bit-ALU with clock to one without
I wrote this VHDL-program vor an ALU and its testbench that is working:ALU-code:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity ALU_CLK is port( Clk : in std_logic; --clock signal InRegA,InRegB : in signed(31 downto 0); --

Implementing ceil function in Xilinx

Implementing ceil function in Xilinx
I would like to take the ceil of the signal in Simulink(Xilinx Library). So, if for instance, the signal value is 1.5, the output would be 2.Any suggestion on how can I implement it in Simulink ?Also, I am keen to understand the approach how for inst

Connecting ports by name in VHDL, UCF-style

Connecting ports by name in VHDL, UCF-style
I have a VHDL entity defined like this:entity RealEntity is port( CLK_50MHZ: in std_logic; LED : out std_logic_vector(3 downto 0) ); end RealEntity;If I also have UCF entries forLED<0>..LED<3>andCLK_50MHZ, then I can compile this entity direct

Is the VHDL package 'IEEE.std_logic_arith' shipped with ghdl?

Is the VHDL package 'IEEE.std_logic_arith' shipped with ghdl?
Im trying to simulate a Xilinx GTXE2 transceiver with GHDL. In GTXE2_CHANNEL.vhd I got an error that 'std_logic_arith' can't be found in library 'ieee'.First off all, here is my machine setup:Windows 7 (pro, x64, german)PowerShell 4.0Python 3.4Xilinx

Why my VHDL code for generating a VGA signal doesn't work

Why my VHDL code for generating a VGA signal doesn't work
I have been going crazy trying to make it work but nothing been on this for the past 6 hours and still didn't solve it :/so this the top modulelibrary IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arith

Verilog - Read bits of register dynamically or using some variable

Verilog - Read bits of register dynamically or using some variable
I want to read 8 bit register bit by bit. i.e first reading 0:3 , then 1:4 , then 2:5 . Reading 4 bits at one time. Below code give error when accessing register bits using integer.module First_Module( clock, reset, enable, counter_out ); // input po

Conditional UCF statements or conditional UCF file inclusion

Conditional UCF statements or conditional UCF file inclusion
Is there a way/workaround to use statements in a UCF file conditionally, or, can UCF files be included into other UCF files conditionally?The problem I'm facing is that I have a top module with a set of generics which conditionally instantiate or rem

Verilog multiple drivers

Verilog multiple drivers
I'm trying to make BCD Counter using verilog that will connected to 7-segment decoder.After I synthesize it, the error occured like this:Multi-source in Unit <BCDcountmod> on signal <BCD0<3>>; this signal is connected to multiple drivers

Why do we use REG in FGPA / VHDL / VIVADO?

Why do we use REG in FGPA / VHDL / VIVADO?
I am programming with Xilinx's vivado in verilog.I was wondering why for some outputs we useregFor examplereg [3:0] encoder_outputwe use that because our 16 to 4 encoder has 4 outputs right? I am assuming that we useregwhenever we need to "STORE SOME

printf in microblaze for hex to char

printf in microblaze for hex to char
I am tryingxil_printf()inside a for loop and feeding it to a SendBuffer over uart. How can print the characters instead of integers ? All it is printing is hex number...uint32_t IRAM; for(Index=0; Index<tsize; Index++){ int sb = Index*sizeof(uint32_t

HOW do I write from a Spartan6 to the Micron external Cellular RAM on the Nexys3 FPGA Board?

HOW do I write from a Spartan6 to the Micron external Cellular RAM on the Nexys3 FPGA Board?
I have looked everywhere, the datasheet, the Xilinx website, digilent, etc. etc. and can't find anything! I was able to use the Adept tool to verify that my Cellular RAM is functioning correctly, but I just can't find any stock VHDL code as a control

Counter with push button switch design using VHDL and Xilinx

Counter with push button switch design using VHDL and Xilinx
I'm very new to VHDL and XILINX ISE. I use the version 13.2 for Xilinx ISE.I want to design a very simple counter with the following inputs:DirectionCountThe count input will be assigned to a button and I want the counter to count up or down accordin

verilog 16b barrel circular shift why it doesn't work?

verilog 16b barrel circular shift why it doesn't work?
module Rotator(shift,lr,in,out); input [3:0] shift; input [15:0] in; input [15:0] out; input lr; wire [15:0] la, ra, lb,rb, lc,rc, ld,rd; //left shift:2^n assign la = shift[0] ? { in[14:0],in[15]} : in; //<<1 assign lb = shift[1] ? { la[13:0],la[15:

Mapping a port in Xilinx Platform Studio and reading it in C

Mapping a port in Xilinx Platform Studio and reading it in C
I'm working in Xilinx Platform Studio, and what I essentially want to do, is have a VHDL module output some values, and then I would like to be able to read that value from another program written in C.I figure what I want to do is map a specific por
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